Senior Staff Engineer/Manager – Design Verification
The verification team is responsible for the verification of IP, Modules, Sub-Systems, System-on-Chip (SoC) (Functional Verification (RTL/PARTL/WRTL); Gate Level Simulation/Verification (GLS) and all aspects of Pre-Silicon Verification); Application & Use Case Verification (in terms of performance, throughput, latency, bandwidth and system use cases), Functional Vector Generation as well as Silicon Bring-up.
What you will do:
- Create and execute verification plans from internal specifications, external IP, and in collaboration with system architects and designers.
- Create and deploy flows for Unit/block and Chip level verification and for coverage metrics collection, for Datapath, Cores (DSP/ARM) and SOC subsystems.
- Architect, design, and troubleshoot Universal Verification Model (UVM) Components, Bus Functional Models (BFM’s), environments etc.
- Develop Synthesizable Verilog, System Verilog Components for Test Bench, and/or integrate UVM components, including analog component models and external components/models into the testbench.
- Work with Analog and Digital team members to debug failures, manage bug tracking, and achieve the high code, functional and system level coverage needed.
- Hold detailed verification plan reviews with cross functional system and design teams.
- Set & practice standards for coding quality.
- Integrate 3rd party Verification IP (VIP) & models into Test Bench and testcases into system level test suites.
- Develop scripts in Python/Perl/TCL/Shell scripts to achieve the objectives.
- Plan, execute and debug of gate level simulations for functional, and power analysis/estimation.
- Plan, develop, and deploy FPGA based verification systems (Xilinx/Protium) to augment and complete verification requirements and support early software development.
- Develop/Debug Functional Test Vectors for ATE (Automatic Test Equipment).
- As the DV lead answer questions and provides mentorship to others.
- Coordinate with other chip, software, and system design teams, as required.
- BS/MS degree in EE/CS with 15+ years of industry experience.
- Knowledge in industry standard processor cores from ARM/Tensilica among other cores.
- Knowledge in industry standard bus protocols such as AMBA/AXI.
- Knowledge of industry standard peripheral interfaces such as DDR, Gigabit Ethernet (GMAC), PCIe, UART, I2C, QSPI etc.
- Ability to read/understand and debug Verilog/System Verilog/VHDL RTL code.
- Experience in Verilog, System Verilog, UVM, OVM, VMM.
- Programming experience in C/C++.
- Solid verification skills involving problem solving, as well as targeted & constrained random testing and debugging.
- Hands on experience with gate level simulations (GLS).
- Experience writing scripts in Perl/Python/Shell/TCL.
Additional value-added skills:
- Familiarity with ISO 26262 Functional Safety required verification process and methods.
- Experience with FPGA based verification/development with Protium.
- MATLAB experience
- Experience with System Verilog Assertions (SVA)
If you are passionate, hardworking, and want to be part of a company that is pushing the boundaries of radar sensing in the automotive industry, then Uhnder is the place for you. Join us in our mission to make a real difference in vehicle and road safety around the world.
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